The present invention relates to a semiconductor device, and more particularly to a silicon-on-insulator semiconductor device.
The silicon-on-insulator semiconductor device is attractive as being capable of easy isolation to devices and latch-up free as well as reduction in junction capacity of source and drain. If, however, a MOS field effect transistor is formed on an ultrathin silicon-on-insulator film having a thickness of not more than 50 nanometers, resistances of the source and drain of the MOS field effect transistor are extremely high, for which reason it is necessary to reduce the resistances of the source and drain of the MOS field effect transistor. In order to reduce the resistances of the source and drain of the MOS field effect transistor, it is effective to form refractory metal silicide layers such as titanium silicide layers in the source and drain regions of the MOS field effect transistor.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a conventional MOS field effect transistor having titanium silicide layers formed on a silicon-on-insulator thin film. A buried oxide film 2 as an insulator is formed on a silicon substrate 1. A silicon-on-insulator film is formed on the buried oxide film 2, wherein the silicon-on-insulator film comprises a p.sup.- -type layer 3 and n+-type layers 7 positioned opposite sides of the p.sup.- -type layer 3. An upper region of the p.sup.- -type layer 3 in the siliconon-insulator film serves as a channel region. The n+-type layers 7 in the silicon-on-insulator film serve as source and drain regions. A gate oxide film 4 is provided on the p.sup.- -type layer 3 in the silicon-on-insulator film. A polysilicon gate electrode 5 is provided on the gate oxide film 4. Titanium silicide layers 8 are provided in upper regions of the polysilicon gate electrode 5 and the source and drain regions of the n+-type layers 7. Side wall oxide films 6 are provided on opposite side walls of the polysilicon gate electrode 5 and the titanium silicide layer 8 on the polysilicon gate electrode 5. Under the side wall oxide films 6, the titanium silicide layers 8 do not extend.
The above MOS field effect transistor on the silicon-on-insulator film may be formed as follows-The silicon-on-insulator film having the predetermined thin thickness is formed on the buried oxide layer 2 by a mesa isolation technique. The silicon-on-insulator film is divided into the p.sup.- -type layer 3 and the n+-type layers 7 by selective ion-implantations of p-type and n-type impurities. The gate oxide film 4 is formed on the p.sup.- -type layer 3. An impurity doped polysilicon layer is formed over the silicon-on-insulator film before the impurity doped polysilicon layer is then patterned to define the polysilicon gate electrode 5. A silicon oxide film is then deposited by a chemical vapor deposition so that the silicon oxide film extends over the polysilicon gate electrode 5 and the n+-type layers 7 in the silicon-on-insulator film. An anisotropic etching to the silicon oxide film is carried out to leave the silicon oxide film only on opposite side walls of the polysilicon gate electrode 5, thereby forming the side wall oxide films 6. A titanium layer having a predetermined thickness is deposited entirely over the polysilicon gate electrode 5, the side wall oxide films 6 and the n+-type layers 7 in the silicon-on-insulator film by sputtering a titanium target. The titanium film is then subjected to a high temperature annealing at about 700.degree. C. in an inert gas atmosphere such as a nitrogen atmosphere to cause a selective silicidation reaction of titanium with silicon over the polysilicon gate electrode 5 and the n+-type layers 7 in the silicon-on-insulator film, whereby C49-structured titanium silicide layers 8 are selectively formed on the polysilicon gate electrode 5 and the n+-type layers 7 in the silicon-on-insulator film, whilst titanium nitride layers are formed over the buried oxide layer 2 and the side wall oxide films 6. The titanium nitride layers are removed by a wet etching. The C49-structured titanium silicide layers 8 are then subjected to a second heat treatment at about 800.degree. C. in an inert gas atmosphere such as a nitrogen atmosphere to cause a phase transition from C49-crystal structure into C54-crystal structure, whereby C54-structured titanium silicide layers 8 are formed in the upper regions of the polysilicon gate electrode 5 and the n+-type layers 7 in the silicon-on-insulator film.
In Proceedings 1995 IEEE International SOI Conference, October 1995, pp. 30-31, there is disclosed one of the above MOS field effect transistors formed on the silicon-on-insulator. FIG. 2 is a fragmentary cross sectional elevation view illustrative of a first type of the conventional MOS field effect transistor having titanium silicide layers formed on a silicon-on-insulator thin film, wherein titanium silicide layers have a thickness of 20 nanometers whilst a silicon-on-insulator has a thickness of 50 nanometers. The titanium silicide layers 8 are thinner than n+-type silicon layers 7 under the titanium silicide layers 8. Namely, a buried oxide film 2 as an insulator is formed on a silicon substrate 1. A silicon-on-insulator film is formed on the buried oxide film 2, wherein the silicon-on-insulator film comprises a p.sup.- -type layer 3 and n+-type layers 7 positioned opposite sides of the p.sup.- -type layer 3. An upper region of the p.sup.- -type layer 3 in the silicon-on-insulator film serves as a channel region. The n+-type layers 7 in the silicon-on-insulator film serve as source and drain regions. A gate oxide film 4 is provided on the p.sup.- -type layer 3 in the silicon-on-insulator film. A polysilicon gate electrode 5 is provided on the gate oxide film 4. Titanium silicide layers 8 arc provided in upper regions of the polysilicon gate electrode 5 and the source and drain regions of the n+-type layers 7. Side wall oxide films 6 are provided on opposite side walls of the polysilicon gate electrode 5 and the titanium silicide layer 8 on the polysilicon gate electrode 5. Under the side wall oxide films 6, the titanium silicide layers 8 do not extend. The silicide layers 8 have a thickness of 20 nanometers whilst the silicon-on-insulator has a thickness of 50 nanometers. The n+-type silicon layers 7 under the titanium silicide layers 8 have a thickness of 30 nanometers. For those reasons, the titanium silicide layers 8 are thinner than n+-type silicon layers 7 under the titanium silicide layers 8.
The above first type of the conventional MOS field effect transistor formed on the silicon-on-insulator substrate has such a structural feature that the titanium silicide layers 8 are thinner than n+-type silicon layers 7 under the titanium silicide layers 8. In this case, an impurity concentration of the channel region is so set as to suppress short channel effects of sub-quarter micron order devices. FIG. 3 is a diagram illustrative of drain current-drain voltage characteristics of the first type conventional MOS field effect transistor applied with various gate voltages of 2.5V, 2.0V, 1.5V, 1.0V and 0.5V. FIG. 3 shows that kink effects appear on the drain current-drain voltage characteristics of the first type conventional MOS field effect transistor. Those kink effects cause remarkable increases in distortion of the device operations. The silicon-on-insulator structure electrically isolates or floats the MOS field effect transistor from the semiconductor substrate, for which reason the increase in drain current of the MOS field effect transistor causes a generation of electron-hole pairs due to impact ionization of carriers under a highly concentrated field at a junction between the drain and channel regions of the MOS field effect transistor. The electrons generated are absorbed into the drain whilst a part of the generated holes is absorbed into the source. Notwithstanding, the remaining holes are accumulated in the channel region. This accumulation of the holes in the channel region causes an increase in potential of the channel region, whereby a threshold voltage of the MOS field effect transistor is dropped. This drop in threshold voltage of the MOS field effect transistor causes rapid increase in the drain current of the MOS field effect transistor at a drain voltage. This rapid increase in the drain current is the result of the kink effect. Every drain current-drain voltage characteristics of the first type conventional MOS field effect transistor applied with various gate voltages of 2.5V, 2.0V, 1.5V, 1.0V and 0.5V show the kink effects.
In IEEE Electron Device Letters, Vol. 13, No. 5, May 1992, pp. 235-237, there is disclosed a second type of the above conventional MOS field effect transistor formed on the silicon-on-insulator. FIG. 4 is a fragmentary cross sectional elevation view illustrative of a second type of the conventional MOS field effect transistor having titanium silicide layers formed on a silicon-on-insulator thin film, wherein source and drain regions in a silicon-on-insulator layer are completely and entirely silicided so that the source and drain regions comprise titanium silicide layers having a thickness of 40 nanometers and the titanium silicide layers as the source and drain regions are in contact directly with the buried oxide layer which electrically isolates the silicon-on-insulator from the semiconductor substrate. Namely, a buried oxide film 2 as an insulator is formed on a silicon substrate 1. A silicon-on-insulator film is formed on the buried oxide film 2, wherein the silicon-on-insulator film comprises a p.sup.- -type layer 3, n+-type layers 7 positioned opposite sides of the p.sup.- -type layer 3 and titanium silicide layers 8-1 positioned opposite sides of the n+-type layers 7. An upper region of the p.sup.- -type layer 3 in the silicon-on-insulator film serves as a channel region. A gate oxide film 4 is provided on the p.sup.- -type layer 3 in the silicon-on-insulator film. A polysilicon gate electrode 5 is provided on the gate oxide film 4. Side wall oxide films 6 are provided on opposite side walls of the polysilicon gate electrode 5 and the titanium silicide layer 8 on the polysilicon gate electrode 5. Under the side wall oxide films 6, the n+-type layers 7 are positioned. A titanium silicide film 8-2 is provided in an upper region of the polysilicon gate electrode 5. The titanium silicide layers 8-1 and 8-2 have a thickness of 40 nanometers which is the same as the silicon-on-insulator layer, whereby the titanium silicide layers 8-1 of the source and drain regions are in contact directly with the buried oxide layer 2. Namely, the source and drain regions in the silicon-on-insulator layer are completely and entirely silicided.
The above second type of the conventional MOS field effect transistor formed on the silicon-on-insulator substrate has such a structural feature that the source and drain regions in the silicon-on-insulator layer are completely and entirely silicided so that the source and drain regions comprise the titanium silicide layers 8-1. In this case, the drain current in the drain current-drain voltage characteristic is reduced by a parasitic resistance of the second type conventional MOS field effect transistor. FIG. 5 is a diagram illustrative of drain current-drain voltage characteristics of the second type conventional MOS field effect transistor applied with various gate voltages of 2.5V, 2.0V, 1.5V, 1.0V and 0.5V. FIG. 5 shows that the drain currents in the drain current-drain voltage characteristics of the second type conventional MOS field effect transistor applied with the various gate voltages of 2.5V, 2.0V, 1.5V, 1.0V and 0.5V are reduced by the parasitic resistance of the second type conventional MOS field effect transistor. These reductions in the drain currents in the drain current-drain voltage characteristics of the second type conventional MOS field effect transistor results in remarkable deteriorations of the high speed performances of the second type conventional MOS field effect transistor Namely, the titanium silicide layers 8-1 are in contact directly with the n+-type regions 7 but only on a section area of the silicon-on-insulator layer, whereby junction areas between the n+-type regions 7 and the titanium silicide layers 8-1 are small and limited into the section area of the silicon-on-insulator layer. This small junction areas between the n+-type regions 7 and the titanium silicide layers 8-1 cause increases in contact resistances between the n+-type regions 7 and the titanium silicide layers 8-1. This increment of the contact resistances between the n+-type regions 7 and the titanium silicide layers 8-1 appears as the parasitic resistance.
In the above circumstances, it had been required to develop a novel silicide layer structure in an ultrathin silicon-on-insulator layer for a silicon-on-insulator sub-quarter micron order MOS field effect transistor, which is free from the above problems.